The present invention generally relates to clock signal generation, and in particular to clock generation and synchronization systems which require handover between multiple reference sources.
Clock generation and synchronization systems are vital in many applications as they provide clock pulses required for synchronizing discrete and/or integrated circuits in many systems, such as telecommunication systems and other digital systems.
In many clock generation systems, a redundant architecture is utilized to meet the requirements on safety and reliability and to increase the mean time between system failure (MTBSF). Redundancy is normally ensured by using multiple clock modules that are interchangeable. With this arrangement, a faulty module can easily be switched out of operation while the remaining and still-functioning modules will maintain proper operation of the system.
In a typical application, a phase-locked loop (PLL) for clock signal generation operates towards a primary reference source, which provides the PLL with a primary reference clock signal. For increased reliability, the PLL has a number of standby reference sources to enable handover from the primary reference source to a standby reference source in case of malfunction such as clock loss or a degrading primary reference clock signal. However, when the operation is switched from one reference source to another and there is a phase difference between the reference clock signals of the two sources, a transient may be introduced into the system. Such a transient may propagate throughout the system so that at least portions of the overall system will be out of synchronization for a certain period of time, thus degrading the performance and reliability of the overall system. Naturally, it is desirable to reduce or eliminate any transients occurring when switching reference sources, and provide a seamless handover between different reference sources.
It is known to use delay elements arranged to compensate for the phase difference between different reference sources. However, delay lines, passive or active, generally have poor temperature and voltage variation stability, and variations in ambient temperature or supply voltage may thus introduce a significant undesirable phase drift. Integrating the delay element in an external control loop provide a better long term stability, but the jitter is increased and open loop conditions are still the same if the control process is terminated at some point. Active (silicon) delay lines generally experience a smallest step zero delay, and they also exhibit a finite accuracy or smallest incremental delay step due to control word size and atomic delay element properties, which in the end limit the tracking accuracy and give a lower bound for the jitter when the phase changes one step.
U.S. Pat. No. 5,638,410 discloses a system for aligning the phase of high-speed clocks in a telecommunication system. The system includes a phase detector for measuring the phase difference between the output signals from a primary stratum clock module and a standby stratum clock module. A microprocessor calculates the time needed to delay the standby clock signal enough to cancel the phase difference, and controls a digital delay line arranged for delaying the standby clock signal accordingly.
U.S. Pat. No. 5,648,964 discloses a master-slave multiplex communication system incorporating two communication devices, each with a data processing unit and a clock processing unit. The data processing unit of the first communication device receives a data signal, and the clock unit of the first device receives a clock in synchronism with the data signal as well as a clock from the second communication device. Correspondingly, the data processing unit of the second communication device receives a data signal, and the clock unit of the second device receives a clock in synchronism with the data signal as well as a clock from the first communication device. Each clock processing unit is configured with a delay circuit for delaying the clock received from the clock unit of the other communication device, a selection circuit for selecting one of the clock signals received by the clock unit, and a PLL for locking to the clock selected by the selection circuit and producing a synchronous clock of a frequency required for the data processing unit. In each communication device, the clock signal selected by the selection circuit of the corresponding clock unit is sent to the other communication device. The data signals from the two communication devices are fed together with their synchronous clocks to a multiplexer, in which the data signals are multiplexed and outputted. The delay circuits are provided for adjusting the phase of the selected clock signals so as to suppress phase variations occurring when the master-slave relationship between the communication devices is changed.
The Japanese Patent Abstract 11008813 A shows a phase locked loop (PLL) circuit arranged for suppressing noise that otherwise would appear on an LCD screen by superimposing a video signal on the control voltage that controls the VCO of the PLL circuit.
The present invention overcomes these and other drawbacks of the prior art arrangements.
It is a general object of the present invention to provide a robust and accurate clock phasing mechanism.
It is a particular object of the invention to provide a phase-locked loop (PLL) based system and method for clock signal generation, which makes it possible to shift the output clock phase of the PLL arbitrary while still maintaining phase lock to the PLL reference. In this respect, a typical application according to the invention would be to provide seamless handover between different reference sources.
These and other objects are met by the invention as defined by the accompanying patent claims.
The general idea according to the invention is to introduce a so-called xe2x80x9cvirtualxe2x80x9d delay in the control loop of the PLL for the purpose of forcing the control loop to shift the phase of the PLL output clock signal, while still maintaining the mandatory phase lock condition of the PLL relative to a primary reference signal, towards a predetermined target phase relation with the primary reference signal.
The addition of an apparent delay, for example in the forward path of the control loop anywhere between the phase detector and the loop filter, forces the control mechanism of the PLL to compensate with a phase shift of equal magnitude but in opposite direction by displacing the output clock phase to maintain the mandatory phase lock condition. It is thus possible to shift the output clock phase of the PLL arbitrary, while maintaining a perfect phase lock to the current PLL reference.
For a typical application of the invention relating to a clock generation system implementing handover between a primary reference clock and a standby reference clock, the phase of the output clock of the PLL is normally shifted towards the phase of the standby reference clock, and when the target phase is reached, the reference clock for the PLL is switched from the primary reference to the standby reference. In this way, switching transients are eliminated and seamless handover is accomplished.
By utilizing a virtual delay, the problems associated with explicit delay elements such as passive or active delay lines are avoided, and a more robust and accurate clock phasing mechanism is obtained.
Preferably, the virtual delay is introduced by superimposing an external phasing control signal in the control loop of the PLL. From a practical point of view, it has turned out to be particularly advantageous to superimpose the phasing control signal on the output signal of the internal phase detector of the PLL.
For reference handover applications, the phasing control signal is normally provided by a phasing loop. The phasing loop has a significantly larger time constant than the control loop of the PLL so as to assure the mandatory phase lock condition of the PLL at all times.
A further advantage offered by the invention is that the virtual delay only depends on relative voltage references. The phase shift of the output clock signal is defined only by the ratio between the phasing voltage and the supply voltage of the PLL. From a control system point of view, such a strategy is superior to and more robust than an absolute value reference strategy.
The invention offers the following advantages:
Robust and accurate clock phasing mechanism;
Seamless handover between reference sources;
Well-defined output clock phase shift, since the virtual delay only depends on relative voltage references; and
Reduced need for explicit delay elements.
Other advantages offered by the present invention will be appreciated upon reading of the below description of the embodiments of the invention.